LDMOS (lateral double-diffused MOS) transistors are quickly replacing bipolar transistors as power devices in intelligent power integrated circuits due to their performance advantage. Minimizing the drain-source resistance when a LDMOS transistor is turned on (Rdson) is important for power and high voltage applications, for minimizing power dissipation, and for purposes of minimizing the chip area utilized by the LDMOS. In order to fabricate a high voltage LDMOS with a short channel having desirable Rdson & breakdown voltage characteristics, it is important to both produce the body implant (or the Drain implant) of the LDMOS device using a provide a deep (high energy) implant process (to sustain high voltages), and also to align the body implant (or the drain implant) to the edge of the gate electrode silicon (herein “polysilicon”) gate (to reduce device footprint, hence lower Rdson).
One typical fabrication technique that is used to produce “self-aligned” implant regions involves forming a polysilicon structure, and then using the polysilicon structure as a mask during the implant diffusion process (i.e., such that the implant region is defined by and therefore aligned with an edge of the polysilicon structure). This technique is effective in standard CMOS fabrication techniques in the production of power CMOS transistors because standard CMOS polysilicon structures are relatively thick (e.g., 0.45 microns) so that the implanted ions do not penetrate through the polysilicon during the implant and enter the underlying substrate. However, deep sub-micron VLSI fabrication processes utilize relatively thin (e.g., 0.2 microns) polysilicon gate structures. These thin polysilicon structures are suitable for producing low voltage CMOS transistors because, the required source/drain diffusions can be produced using low energy implant processes, but may not be suitable for producing LDMOS transistors or other structures that require deep implant regions self-aligned to the thin polysilicon. That is, using polysilicon gate structures as masks requires matching the polysilicon thickness to the implant energy. If the implant diffusion process is performed at a high enough energy, the implanted ions will penetrate the polysilicon and diffuse into the (e.g., channel) region of the substrate located below the polysilicon, thus causing failure of the VLSI device. This is a particular problem in the fabrication of LDMOS devices because the body implant (or the Drain implant) require a high energy implant, to sustain high diode breakdown.
Another fabrication technique that may be used to form deep (high energy) body implants (or Drain implants) using VLSI fabrication processes involves forming the deep implants prior to forming the polysilicon structures. A problem with this non-self aligned approach is that precise alignment of the polysilicon edge to the body implant (or Drain implant) is difficult to achieve, which produces an inconsistent and hence undesirable drain-source resistance Rdson.
None of the approaches described above produce a suitable VLSI LDMOS transistor. The “self-aligned” prior art approach provides the proper alignment between the implant and polysilicon gate, but cannot be used to produce the required body implant (or the Drain implant). Conversely, the non-self-aligned approach provides sufficiently deep body implants (or Drain implants), but does not provide certainty of proper alignment between the implant and gate.
Thus, what is needed is a method for fabricating LDMOS devices using VLSI fabrication techniques that both facilitates the use of the thinner polysilicon gate structures associated with VLSI technology, and provides LDMOS body/Drain implant regions that are both sufficiently deep and reliably aligned with corresponding polysilicon gate structures.